Performance gains in high performance logic circuits rely on increasing the ‘on’ current without increasing the ‘off’ current. As device dimensions are scaled, performance gains are more difficult to achieve. One particular aspect of scaling involves reducing the physical thickness of the gate oxide. For a given gate voltage, an electric field is established across the gate oxide. If the gate oxide is reduced, then the magnitude of the electric field increases for the same gate voltage. In the case of a pFET device, a negative voltage is applied to the gate to turn ‘on’ the device. When the device is in the ‘on’ state, the channel becomes inverted with respect to its majority carrier type. As inversion charges in the channel increase, the gate becomes depleted of its majority carrier.
Depletion of charge carriers at, or near, the interface between the gate oxide/polySi gate (known as the poly depletion effect) has been a problem for complementary metal oxide semiconductor (CMOS) devices, and in particular for pFET devices. The depletion causes a virtual increase in gate dielectric thickness thereby adversely impacting device performance. The effect of the depletion becomes increasingly important with progressively decreasing gate oxide thickness because the poly depletion effect increase becomes fractionally higher.
In the traditional CMOS process, poly-Si gates are doped during the self-aligned source/drain implantation and they are activated during a subsequent activation anneal step. The implantation energy used in the prior art process is selected so that the dopant atoms will not penetrate to deeply within the poly-Si gate electrode. As such, there is a relatively small concentration (on the order of about 1018 atoms/cm3 or less) of dopant atoms that can reach the gate dielectric/poly-Si gate interface by implantation. Although diffusion can bring more dopant atoms to the gate dielectric/poly-Si interface, the doping concentration at the interface is always the lowest. Moreover, the dopant atoms present at the gate dielectric/poly-Si gate interface are unevenly distributed.
In order to circumvent the poly depletion effect mentioned above, it is desired to have a high concentration (on the order of about 1019 atoms/cm3 or greater) of activated dopants at the gate dielectric/poly-Si gate interface. The nature of the prior art implantation profile makes it hard to precisely place a large concentration of dopants close to this interface.
In view of the above, a method is needed that is capable of providing a CMOS structure having a high concentration of dopant atoms at the interface between the gate dielectric and the overlying poly-Si gate.